Search - VHDL carrier

[Post-TeleCom sofeware systems] mfsk

Description: vhdl mfsk 多进制数字频率调制(MFSK)也称多元调频或多频制。MFSK系统是 2FSK(二频键控)系统的推广，该系统有 M个不同的载波频率可供选择．每一个载波频率对应一个 M进制码元信息，即用多个频率不同的正弦波分别代表不同的数字信号，在某一码元时间内只发送其中一个频率。-vhdl mfsk M-ary digital frequency modulation (MFSK), also known as multi-frequency or multi-frequency system. MFSK system is 2FSK (b Frequency Shift Keying) system, the promotion, the system has M different carrier frequencies to choose from. Each carrier frequency corresponds to an M-band meta-information code, which uses a number of different sine wave frequency, respectively, representing different digital signal, in a symbol time to send only one frequency.
Platform: | Size: 1024 | Author: mzizai | Hits:

[Communication] TheResearchofSychronizationTechnologyinReceiver.ra

Description: 本文首先介绍了数字接收机中同步技术，包括载波同步和符号同步。同步算法主要可以分为两大类:现行的开环算法和传统的闭环算法。接着研究了一些典型的载波同步算法和符号同步算法。 -This paper first introduces the digital receiver synchronization techniques, including carrier synchronization and symbol synchronization. Synchronization algorithm can be divided into two main categories: the existing open-loop algorithm and the traditional closed-loop algorithm. Then study some typical carrier synchronization algorithm and symbol synchronization algorithm.
Platform: | Size: 2898944 | Author: 萝卜 | Hits:

[Program doc] FPGAImplementationof16QAMDemodulator

Description: 描述了一个用于微波传输设备的16QAM接收机解调芯片的FPGA实现,芯片集成了定时恢复、载波恢复和自适应盲判决反馈均衡器(DFE),采用恒模算法(CMA)作为均衡算法。芯片支持高达25M波特的符号速率,在一片EP1C12Q240C8(ALTERA)上实现,即将用于量产的微波传输设备中。 -Describes a microwave transmission equipment for 16QAM receiver demodulator chip FPGA realization of an integrated chip timing recovery, carrier recovery and blind adaptive decision feedback equalizer (DFE), using constant modulus algorithm (CMA) as the equalization algorithm. Chip supports up to 25M baud symbol rate, in the midst of EP1C12Q240C8 (ALTERA) achieved for the upcoming production of microwave transmission equipment.
Platform: | Size: 281600 | Author: 萝卜 | Hits:

[Applications] infrared_transmitter

Description: 自定义编码的红外发射器，采用汉明纠错编码。接收方可实现一位误码的纠错。38KHz发射载波调制，配合红外发射二级管可实现5－10米的数据通信与遥控。-Custom-coded infrared transmitters using Hamming error correction coding. Receive only realize a bit error correction. 38KHz launch carrier modulation, with the infrared emission diode can realize 5-10 m data communication with the remote control.
Platform: | Size: 358400 | Author: M | Hits:

[Communication-Mobile] qpsk

Description: 载波同步是QPSK信号相干解调的一项关键技术。-Carrier synchronization signal coherent QPSK demodulation is a key technology.
Platform: | Size: 262144 | Author: 王天权 | Hits:

[VHDL-FPGA-Verilog] AM

Description: FPGA内AM调制工程。内带调制波、载波生成。关键词：FPGA verilog AM DDS-AM modulation works within the FPGA. Within the band modulation wave generated carrier. Key words: FPGA verilog AM DDS
Platform: | Size: 1687552 | Author: baixiangzhou | Hits:

[GPS develop] carrier_nco

Description: 通信电路中产生载波的电路，可应用于GPS中的捕获和跟踪环路。-Generated carrier communication circuit of the circuit, can be applied to GPS in the capture and tracking loop.
Platform: | Size: 2048 | Author: Li Gengmin | Hits:

[VHDL-FPGA-Verilog] Simulation-and-FPGA-Implementation-of-DigitalDBPSK

Description: 文章介绍了系统的硬件电路原理与具体实现方法，其中主要包括载波恢复电路，PN 码捕获电路和跟踪电路，并针对Xilinx 公司FPGA 的特点，对各电路的实现进行优化设计，在不影响系统稳定性和精度的前提下，减少硬件资源消耗，提高硬件利用率。设计利用Verilog 硬件描述语言完成，通过后仿真验证电路正确性，并给出综合结果。-This paper introduces the system' s hardware circuit principle and the specific implementation methods, which mainly include the carrier recovery circuit, PN code acquisition circuit and track circuits, and FPGA for Xilinx company characteristics, the implementation of the circuit to optimize the design, without affecting the system stability and precision under the premise of reduced hardware resource consumption, improve hardware utilization. Designed using Verilog Hardware Description Language finish, after the passage of the correctness of circuit simulation, and give General results.
Platform: | Size: 1007616 | Author: mayuan | Hits:

[OS program] costas

Description: 科斯塔斯载波同步的实现。采用了V_LOG代码编写~~~~ 可以直接编译使用-Costas carrier synchronization is achieved. Coding used V_LOG ~ ~ ~ ~ can direct the compiler to use
Platform: | Size: 5120 | Author: 刘伟 | Hits:

[VHDL-FPGA-Verilog] gps_tracking

Description: 澳大利亚新南威尔士大学研究的GPS接收机的FPGA跟踪模块的.v程序，包括载波跟踪环路、码跟踪环路、通道累加等模块。-The University of New South Wales, Australia, the study of the FPGA tracking GPS receiver module. V procedures, including the carrier tracking loop, code tracking loop, the channel accumulation modules.
Platform: | Size: 14336 | Author: Jerry | Hits:

[TCP/IP stack] terabit_ethernet

Description: TERABIT ETHERNET 具体介绍包括Time-Space Carrier Sense Multiple Access (CSMA/TS)-TERABIT ETHERNET introduction （Time-Space Carrier Sense Multiple Access (CSMA/TS)）
Platform: | Size: 691200 | Author: zhouli | Hits:

[VHDL-FPGA-Verilog] cotas

Description: Costas环是用来解调双边带抑制载波信号的,也是二相或四相移相键控信号解调的专用环路-Costas loop is used to double sideband suppressed carrier signal demodulation, and also two-phase or four phase shift keying signal demodulation of the special loop
Platform: | Size: 3072 | Author: 陈华 | Hits:

[VHDL-FPGA-Verilog] Rake-receive

Description: 本文介绍的一种基于多载波扩频通信的Rake接收机工作原理以及设计思想，并用FPGA技术加以实现-This article describes a multi-carrier spread spectrum based communication works as well as Rake receiver design and implementation with FPGA technology to
Platform: | Size: 232448 | Author: 杨帆 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: EDA技术以EDA软件工具为开发环境，以可编程逻辑器件为实验载体，实现源代码编程和仿真功能。VHDL作为一种标准化的硬件描述语言用于描述数字系统的结构、行为、功能和接口。本设计提出了一种基于VHDL语言的编码器和译码器的实现方法。编码器与译码器是计算机电路中基本的器件，本课程设计采用EDA技术设计编码和译码器。编码器由8线-3线优先编码器作为实例代表，译码器则包含3线-8线译码器和2线-4线译码器两个实例模块组成。课程设计采用硬件描述语言VHDL把电路按模块化方式进行设计，然后进行编程、时序仿真和分析等。课程设计结构简单，使用方便，具有一定的应用价值。 -EDA technology take the EDA software as tools for the development of the environment,programmable logic devices in experimental carrier,the realiztion of the source code programming and simulation. The VHDL as a standardized hardware description language used to describe the struction of digital systems,behavior,function and interface. The paper proposes a method for encoder and decoder based on the VHDL language.Encoder and decoder is a basic computer circuit devices.This Curriculum design by EDA design encoder and decoder.Encoders from 8- 3 priority encoder for example,and decoder includes 3- 8 decoder and the 2- 4 examples of the two decoder modules.And then to program, the timing simulation and analysis.Curriculum design, simple structure, easy to use and has a value.
Platform: | Size: 797696 | Author: pear | Hits:

[VHDL-FPGA-Verilog] Costas

Description: 介绍了某直接序列扩频、QPSK 调制系统接收通道中四相 Costas 载波跟踪环的原理及其基于 DSP+FPGA 的实现-Introduced a direct-sequence spread spectrum, QPSK modulation system, receive path Costas carrier tracking loop four-phase principle and its implementation based on DSP+ FPGA
Platform: | Size: 562176 | Author: fy | Hits:

[Other] add-recode-vhdl

Description: 基于VHDL编写的地址译码器，硬件描述语言VHDL为主要设计手段，以可编程逻辑器件为实现载体，设计方案中，从循环码编译码的原理出发，论证了BCH码编译码系统的设计方案，并利用VHDL语言加以实现。所设计的系统可以完成BCH码编码以及两位错码的纠错译码。-Based on the address decoder in VHDL hardware description language VHDL design as the main means to achieve carrier programmable logic devices, design, coding-decoding cycle from starting principle is demonstrated BCH code encoding and decoding system design and to be implemented using VHDL language. The system can be designed to complete the error correction coding and decoding BCH error code two.
Platform: | Size: 25600 | Author: 吴家 | Hits:

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